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ADE7518
Table 7. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter
t SL
t SH
Description
SCLK low pulse width
SCLK high pulse width
Min
2 SPIR × t CORE1
2 SPIR × t CORE1
Typ
(SPIR + 1) × t CORE1
(SPIR + 1) × t CORE1
Max
Unit
ns
ns
t DAV
t DOSU
t DSU
t DHD
t DF
t DR
t SR
t SF
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
0
t CORE1
19
19
19
19
3 × t CORE1
75
ns
ns
ns
ns
ns
ns
ns
ns
1
t CORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); t CORE = 2 CD /4.096 MHz.
SCLK
(SPICPOL = 0)
t SH
t SL
SCLK
(SPICPOL = 1)
t DAV
t SR
t SF
MOSI
t DOSU
t DF
t DR
MSB
BITS [6:1]
LSB
MISO
MSB IN
t DSU
t DHD
BITS [6:1]
LSB IN
Figure 5. SPI Master Mode Timing (SPICPHA = 0)
Rev. 0 | Page 11 of 128
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